Chip-on-board and board-on-chip (BOC) techniques are used to attach semiconductor dies to an interposer or other carrier substrate such as a printed circuit board (PCB). Attachment can be achieved through flip chip attachment, wirebonding, or tape automated bonding (“TAB”).
Flip chip attachment typically utilizes ball grid array (BGA) technology. The BGA component (die) includes conductive external contacts, typically in the form of solder balls or bumps, arranged in a grid pattern on the active surface of the die, which permit the die to be flip chip mounted to an interposer or other carrier substrate (e.g., PCB).
In a flip chip attachment, the balls of the BGA component are aligned with terminals on the carrier substrate, and connected by reflowing the solder balls. The solder balls can be replaced with a conductive polymer that is cured. A dielectric underfill is then interjected between the flip chip die and the surface of the carrier substance to embed the solder balls and mechanically couple the BGA component to the carrier substrate.
Wirebonding and TAB attachment generally involve attaching a die by its backside to the surface of a carrier substrate with an appropriate adhesive (e.g., epoxy) or tape. With wirebonding, bond wires are attached to each bond pad on the die and bonded to a corresponding terminal pad on the carrier substrate (e.g., interposer). With TAB, ends of metal leads carried on a flexible insulating tape such as a polyimide, are attached to the bond pads on the die and to the terminal pads on the carrier substrate. A dielectric (e.g., silicon or epoxy) is generally used to cover the bond wires or metal tape leads to prevent damage.
High performance, low cost, increased miniaturization of components, and greater packaging density of integrated circuits have long been goals of the computer industry. One method of increasing integrated circuit density while reducing package size and height is to stack dies vertically. Different approaches to packaging have been pursued to provide stacked die devices.
One such example of a stacked die to lower wire bond loop height is depicted in FIG. 1, shown as an encapsulated package 10 comprising a flip chip mounted on a chip-on-board (“FC-on-chip”). As shown, the package 10 includes a flip chip die 12 mounted via solder bumps 13 with the active surface 16 facing down onto the active surface 18 of a bottom die (chip-on-board) 20, which in turn, is mounted with an adhesive tape or paste 22 onto an interposer substrate 24. Bonding wires 26 connect the bond pads 28 on the bottom die 20 to lead or trace ends 30 on the interposer 24. The interposer 24 includes solder balls 32 for mounting the encapsulated package (component) 10 onto a substrate, e.g., motherboard, PCB (not shown).
Flip chip attachment has provided improved electrical performance and allowed greater packaging density. However, developments in ball grid array technology have produced arrays in which the balls are made smaller and with tighter pitches. As the balls become smaller and are set closer together, it poses problems for the mutual alignment of the conductive bumps 13 on the flip chip die 12 with the bond pads 28 on the bottom die 20, requiring a metal reroute or redistribution layer (RDL) 34 disposed as an intermediate layer on the surface of the bottom die 20. The RDL 34 effects an electrical interconnection (redistribution) between the bond pads 14 on the flip chip die 12 to the bond pads 28 on the bottom die 20 for die attachment and wire bonding to the substrate. If the bond pads 14 on the flip chip die 12 can be wafer bumped, for example, by stencil printing, electrolytic plating or electroless plating, an RDL on the flip chip die 12 may not be necessary, and the flip chip die 12 can be directly bonded to the bottom die 20 through an RDL 34 disposed on the surface of the bottom die 20, as schematically depicted in FIG. 1A, whereby the solder bumps/balls 13 on the flip chip die 12 contact the bond pads 35 of the RDL 34 on the bottom die 20. However, if the pitch of the bond pads 14 is tight, it may not be possible to wafer bump the bond pads 14 (e.g., by stencil printing, electrolytic plating, etc), and additional RDL processing on the flip chip die 12 itself may be required. The RDL 34 functions to provide electrical connection to accommodate the flip chip die 12 in either of these approaches.
Fabricating an FC-on-chip can also lead to high costs and process difficulties. For Example, a flip chip mounter is required to accurately align the flip chip die 12 to the bottom die 20. Another drawback is that damage can occur to the active surface 18 of the bottom die 20 during an underfilling process onto the active surface 18, and a molding filler can fail to flow into voids between the dies if the gap is too small.
In view of these and other deficiencies in conventional methods for fabricating stacked die modules, improvements in fabrication methods are desirable.